altera pin assignment

• Altera Manuals
• Computer Hardware
• tPad DE2-115
• User manual

Altera DE2-115 User Manual

• User manual (43 pages)
• page of 116 Go / 116

Table of Contents

Chapter 7 appendix, chapter 1 de2-115 package.

• Package Contents
• The DE2-115 Board Assembly
• Getting Help

Chapter 2 Introduction of the Altera DE2-115 Board

• Layout and Components
• Block Diagram of the DE2-115 Board
• Power-Up the DE2-115 Board

Chapter 3 DE2-115 Control Panel

• Control Panel Setup
• Controlling the Leds, 7-Segment Displays and LCD Display
• Switches and Push-Buttons
• Sdram/Sram/Eeprom/Flash Controller and Program-Mer
• USB Monitoring
• PS/2 Device
• Communication
• IR Receiver
• Overall Structure of the DE2-115 Control Panel

Chapter 4 Using the DE2-115 Board

• Configuring the Cyclone IV E FPGA
• Using Push-Buttons and Switches
• Using the 7-Segment Displays
• Clock Circuitry
• Using the LCD Module
• High Speed Mezzanine Card
• Using the Expansion Header
• Using 14-Pin General Purpose I/O Connector
• Using the 24-Bit Audio CODEC
• Serial Port
• PS/2 Serial Port
• Gigabit Ethernet Transceiver
• Implementing a TV Encoder
• Using the USB Interface
• Using SRAM/SDRAM/FLASH/EEPROM/SD Card

Chapter 5 DE2-115 System Builder

• Introduction
• General Design Flow
• Using DE2-115 System Builder
• System Configuration

Chapter 6 Examples of Advanced Demonstrations

• DE2-115 Factory Configuration
• TV Box Demonstration
• USB Paintbrush
• A Karaoke Machine
• SD Card Demonstration
• SD Card Music Player
• PS/2 Mouse Demonstration
• IR Receiver Demonstration
• Music Synthesizer Demonstration
• Audio Recording and Playing
• Web Server Demonstration
• Revision History
• Copyright Statement

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Quick Links

• 1 Layout and Components
• 2 Controlling the Leds, 7-Segment Displays and Lcd Display
• 3 Switches and Push-Buttons
• 4 Using Push-Buttons and Switches
• 5 Using Leds
• 6 Using the 7-Segment Displays
• Download this manual

Related Manuals for Altera DE2-115

Summary of Contents for Altera DE2-115

Page 2: table of contents.

• Page 3 Chapter 5 DE2-115 System Builder ..............70 5.1 Introduction ............................70 5.2 General Design Flow .......................... 70 5.3 Using DE2-115 System Builder ......................71 Chapter 6 Examples of Advanced Demonstrations ..........77 6.1 DE2-115 Factory Configuration ......................77 6.2 TV Box Demonstration ........................78 6.3 USB Paintbrush ..........................

Page 4: Chapter 7 Appendix

Page 5: de2-115 package.

• Page 6  Bag of six rubber (silicon) covers for the DE2-115 board stands. The bag also contains some extender pins, which can be used to facilitate easier probing with testing equipment of the board‟s I/O expansion headers.  Clear plastic cover for the board.

Page 7: Getting Help

Page 8: introduction of the altera de2-115 board.

• Page 9 Figure 2-2 The DE2-115 board (bottom view) The DE2-115 board has many features that allow users to implement a wide range of designed circuits, from simple circuits to various multimedia projects. The following hardware is provided on the DE2-115 board: ...

Page 10: Block Diagram Of The De2-115 Board

• Page 11 Following is more detailed information about the blocks in Figure 2-3:  Cyclone IV EP4CE115F29 device  114,480 LEs  432 M9K memory blocks  3,888 Kbits embedded memory  4 PLLs  JTAG and AS mode configuration  EPCS64 serial configuration device ...
• Page 12  40-pin expansion port o Configurable I/O standards (voltage levels:3.3/2.5/1.8/1.5V)  VGA-out connector o VGA DAC (high speed triple DACs)  DB9 serial connector for RS-232 port with flow control  PS/2 mouse/keyboard  Three 50MHz oscillator clock inputs  SMA connectors (external clock input/output) ...

Page 13: Power-Up The De2-115 Board

• Page 14  You can also connect a microphone to the microphone-in connector on the DE2-115 board; your voice will be mixed with the music playing on the audio player Figure 2-4 The default VGA output pattern...

Page 15: De2-115 Control Panel

• Page 16 LEDs and observing the result on the DE2-115 board. Figure 3-1 The DE2-115 Control Panel 3-2. The “Control Circuit” that The concept of the DE2-115 Control Panel is illustrated in Figure performs the control functions is implemented in the FPGA board. It communicates with the Control Panel window, which is active on the host computer, via the USB Blaster link.

Page 17: Controlling The Leds, 7-Segment Displays And Lcd Display

• Page 18 Figure 3-4. From the window, directly use the left-right arrows to control the 7-SEG patterns on the DE2-115 board which are updated immediately. Note that the dots of the 7-SEGs are not enabled on DE2-115 board. Figure 3-4 Controlling 7-SEG display...

Page 19: Switches And Push-Buttons

Page 20: sdram/sram/eeprom/flash controller and program-mer.

• Page 21 Figure 3-7 Accessing the SDRAM A 16-bit word can be written into the SDRAM by entering the address of the desired location, specifying the data to be written, and pressing the Write button. Contents of the location can be read by pressing the Read button.

Page 22: Usb Monitoring

Page 23: ps/2 device, page 24: sd card, page 25: vga, page 26: hsmc, page 27: ir receiver, page 28: overall structure of the de2-115 control panel.

• Page 29 Figure 3-15 The block diagram of the DE2-115 control panel...

Page 30: Using The De2-115 Board

• Page 31 The sections below describe the steps used to perform both JTAG and AS programming. For both methods the DE2-115 board is connected to a host computer via a USB cable. Using this connection, the board will be identified by the host computer as an Altera USB Blaster device. The process for installing on the host computer the necessary software device driver that communicates with the USB Blaster is described in the tutorial “Getting Started with Altera’s DE2-115 Board”...
• Page 32  Configure the JTAG programming circuit by setting the RUN/PROG slide switch (SW19) to the RUN position (See Figure 4-4)  Connect the supplied USB cable to the USB Blaster port on the DE2-115 board (See Figure 2-1)  The FPGA can now be programmed by using the Quartus II Programmer to select a configuration bit stream file with the .sof filename extension...

Page 33: Using Push-Buttons And Switches

• Page 34 Schmitt Trigger Debounced Figure 4-7 Switch debouncing There are also 18 slide switches on the DE2-115 board (See Figure 4-8). These switches are not debounced, and are assumed for use as level-sensitive data inputs to a circuit. Each switch is connected directly to a pin on the Cyclone IV E FPGA.

Page 35: Using Leds

• Page 36 Table 4-1 Pin Assignments for Slide Switches Signal Name FPGA Pin No. Description I/O Standard SW[0] PIN_AB28 Slide Switch[0] Depending on JP7 SW[1] PIN_AC28 Slide Switch[1] Depending on JP7 SW[2] PIN_AC27 Slide Switch[2] Depending on JP7 SW[3] PIN_AD27 Slide Switch[3] Depending on JP7 SW[4] PIN_AB27...

Page 37: Using The 7-Segment Displays

• Page 38 HEX0[5] PIN_J22 Seven Segment Digit 0[5] Depending on JP7 HEX0[6] PIN_H22 Seven Segment Digit 0[6] Depending on JP7 HEX1[0] PIN_M24 Seven Segment Digit 1[0] Depending on JP7 HEX1[1] PIN_Y22 Seven Segment Digit 1[1] Depending on JP7 HEX1[2] PIN_W21 Seven Segment Digit 1[2] Depending on JP7 HEX1[3] PIN_W22...

Page 39: Clock Circuitry

Page 40: using the lcd module, page 41: high speed mezzanine card.

• Page 42 I/O standard between DE2-115 HSMC connector pins and daughter card system. For example, if the I/O standard of HSMC pins on DE2-115 board is set to 1.8V, a daughter card with 3.3V I/O standard may not work properly on DE2-115 board due to I/O standard mismatch.
• Page 43 Figure 4-14 LVDS interface on HSMC connector and Cyclone IV E FPGA Table 4-9 Pin Assignments for HSMC connector FPGA Pin Signal Name Description I/O Standard HSMC_CLKIN0 PIN_AH15 Depending Dedicated clock input on JP6 HSMC_CLKIN_N1 PIN_J28 Depending LVDS RX or CMOS I/O or differential clock input on JP7 HSMC_CLKIN_N2 PIN_Y28...
• Page 44 on JP7 HSMC_RX_D_N[1] PIN_C27 Depending LVDS RX bit 1n or CMOS I/O on JP7 HSMC_RX_D_N[2] PIN_E26 Depending LVDS RX bit 2n or CMOS I/O on JP7 HSMC_RX_D_N[3] PIN_G26 Depending LVDS RX bit 3n or CMOS I/O on JP7 HSMC_RX_D_N[4] PIN_H26 Depending LVDS RX bit 4n or CMOS I/O on JP7...
• Page 45 HSMC_RX_D_P[7] PIN_M25 Depending LVDS RX bit 7 or CMOS I/O on JP7 HSMC_RX_D_P[8] PIN_R25 Depending LVDS RX bit 8 or CMOS I/O on JP7 HSMC_RX_D_P[9] PIN_T25 Depending LVDS RX bit 9 or CMOS I/O on JP7 HSMC_RX_D_P[10] PIN_U25 Depending LVDS RX bit 10 or CMOS I/O on JP7 HSMC_RX_D_P[11] PIN_L21 Depending...

Page 46: Using The Expansion Header

• Page 47 GND pins. Figure 4-15 shows the I/O distribution of the GPIO connector. The maximum power consumption of the daughter card that connects to GPIO port is shown in Table 4-10. Figure 4-15 GPIO Pin Arrangement Table 4-10 Power Supply of the Expansion Header Supplied Voltage Max.
• Page 48 The voltage level of the I/O pins on the expansion headers can be adjusted to 3.3V, 2.5V, 1.8V, or 1.5V using JP6 (The default value is 3.3V, see Figure 4-17). Because the expansion I/Os are connected to Bank 4 of the FPGA and the VCCIO voltage (VCCIO4) of this bank is controlled by the header JP6, users can use a jumper to select the input voltage of VCCIO4 to 3.3V, 2.5V, 1.8V, and 1.5V to control the voltage level of the I/O pins.
• Page 49 I/O standard between DE2-115 GPIO connector pins and daughter card system. For example, if the I/O standard of GPIO pins on DE2-115 board is set to 1.8V, a daughter card with 3.3V I/O standard may not work properly on the DE2-115 board due to I/O standard mismatch.
• Page 50 Figure 4-19 Using Emulated LVDS on GPIO Table 4-12 Pin Assignments for Expansion Headers Signal Name FPGA Pin No. Description I/O Standard GPIO[0] PIN_AB22 GPIO Connection DATA[0] Depending on JP6 GPIO[1] PIN_AC15 GPIO Connection DATA[1] Depending on JP6 GPIO[2] PIN_AB21 GPIO Connection DATA[2] Depending on JP6 GPIO[3]...

Page 51: Using 14-Pin General Purpose I/O Connector

Page 52: using vga.

• Page 53 Note: The RGB data bus on DE2-115 board is 8 bit instead of 10 bit on DE2/DE2-70 board. Figure 4-22 VGA horizontal timing specification Table 4-14 VGA Horizontal Timing Specification VGA mode Horizontal Timing Spec Configuration Resolution(HxV) a(us) b(us) c(us)

Page 54: Using The 24-Bit Audio Codec

Page 55: serial port, page 56: ps/2 serial port, page 57: gigabit ethernet transceiver.

• Page 58 You will need to perform a hardware reset after any change for enabling new settings. Table 4-21 Table 4-22 describe the working mode settings for ENET0 PHY (U8) and ENET1 PHY (U9) respectively. In addition, it is dynamically configurable to support 10Mbps, 100Mbps (Fast Ethernet) or 1000Mbps (Gigabit Ethernet) operation using standard Cat 5e UTP cabling.
• Page 59 Table 4-22 Jumper Settings for Working Mode of ENET1 (U9) JP2 Jumper Settings ENET1 PHY Working Mode Short Pins 1 and 2 RGMII Mode Short Pins 2 and 3 MII Mode Table 4-23 Pin Assignments for Fast Ethernet Signal Name FPGA Pin No.
• Page 60 Ethernet clock source 3.3V The DE2-115 board is equipped with an Analog Device ADV7180 TV decoder chip. The ADV7180 is an integrated video decoder that automatically detects and converts a standard analog baseband television signals (NTSC, PAL, and SECAM) into 4:2:2 component video data compatible with the 8-bit ITU-R BT.656 interface standard.

Page 61: Tv Decoder

Page 62: using the usb interface, page 63: using ir, page 64: using sram/sdram/flash/eeprom/sd card.

• Page 65 Figure 4-34 Connections between FPGA and SDRAM  FLASH The board is assembled with 8MB of flash memory using an 8-bit data bus. The device uses 3.3V CMOS signaling standard. Because of its non-volatile property, it is usually used for storing software binaries, images, sounds or other media.
• Page 66 Many applications use a large external storage device, such as SD Card or CF card, for storing data. The DE2-115 board provides the hardware needed for SD Card access. Users can implement custom controllers to access the SD Card in SPI mode and SD Card 4-bit or 1-bit mode.
• Page 67 Figure 4-37 Connections between FPGA and SD Card Socket Table 4-27 SRAM Pin Assignments Signal Name FPGA Pin No. Description I/O Standard SRAM_ADDR[0] PIN_AB7 SRAM Address[0] 3.3V SRAM_ADDR[1] PIN_AD7 SRAM Address[1] 3.3V SRAM_ADDR[2] PIN_AE7 SRAM Address[2] 3.3V SRAM_ADDR[3] PIN_AC7 SRAM Address[3] 3.3V SRAM_ADDR[4] PIN_AB6...
• Page 68 SRAM_DQ[7] PIN_AF7 SRAM Data[7] 3.3V SRAM_DQ[8] PIN_AD1 SRAM Data[8] 3.3V SRAM_DQ[9] PIN_AD2 SRAM Data[9] 3.3V SRAM_DQ[10] PIN_AE2 SRAM Data[10] 3.3V SRAM_DQ[11] PIN_AE1 SRAM Data[11] 3.3V SRAM_DQ[12] PIN_AE3 SRAM Data[12] 3.3V SRAM_DQ[13] PIN_AE4 SRAM Data[13] 3.3V SRAM_DQ[14] PIN_AF3 SRAM Data[14] 3.3V SRAM_DQ[15] PIN_AG3 SRAM Data[15]...
• Page 69 DRAM_DQ[16] PIN_M8 SDRAM Data[16] 3.3V DRAM_DQ[17] PIN_L8 SDRAM Data[17] 3.3V DRAM_DQ[18] PIN_P2 SDRAM Data[18] 3.3V DRAM_DQ[19] PIN_N3 SDRAM Data[19] 3.3V DRAM_DQ[20] PIN_N4 SDRAM Data[20] 3.3V DRAM_DQ[21] PIN_M4 SDRAM Data[21] 3.3V DRAM_DQ[22] PIN_M7 SDRAM Data[22] 3.3V DRAM_DQ[23] PIN_L7 SDRAM Data[23] 3.3V DRAM_DQ[24] PIN_U5 SDRAM Data[24]...
• Page 70 FL_ADDR[15] PIN_Y10 FLASH Address[15] 3.3V FL_ADDR[16] PIN_AA8 FLASH Address[16] 3.3V FL_ADDR[17] PIN_AH12 FLASH Address[17] 3.3V FL_ADDR[18] PIN_AC12 FLASH Address[18] 3.3V FL_ADDR[19] PIN_AD12 FLASH Address[19] 3.3V FL_ADDR[20] PIN_AE10 FLASH Address[20] 3.3V FL_ADDR[21] PIN_AD10 FLASH Address[21] 3.3V FL_ADDR[22] PIN_AD11 FLASH Address[22] 3.3V FL_DQ[0] PIN_AH8 FLASH Data[0]...

Page 71: Chapter 5 De2-115 System Builder

Page 72: using de2-115 system builder.

• Page 73  Input Project Name Input project name as show in Figure 5-3. Project Name: Type in an appropriate name here, it will automatically be assigned as the name of your top-level design entity. Figure 5-3 The DE2-115 Board Type and Project Name...

Page 74: System Configuration

• Page 75 The “Prefix Name” is an optional feature which denotes the prefix pin name of the daughter card assigned in your design. Users may leave this field empty.  HSMC Expansion Users can connect HSMC-interfaced daughter cards onto HSMC located on the DE2-115 board shown in Figure 5-6.
• Page 76 The “Prefix Name” is an optional feature that denotes the pin name of the daughter card assigned in your design. Users may leave this field empty.  Project Setting Management The DE2-115 System Builder also provides functions to restore default setting, loading a setting, and saving users‟ board configuration file shown in Figure 5-7.
• Page 77  Project Generation When users press the Generate button, the DE2-115 System Builder will generate the corresponding Quartus II files and documents as listed in the Table 5-1: Table 5-1 The files generated by DE2-115 System Builder Filename Description <Project name>.v Top level verilog HDL file for Quartus II <Project name>.qpf...

Page 78: Chapter 6 Examples Of Advanced Demonstrations

Page 79: tv box demonstration.

• Page 80 4:3 aspect ratio o Non-progressive video  Connect the VGA output of the DE2-115 board to a VGA monitor (both LCD and CRT type of monitors should work)  Connect the audio output of the DVD player to the line-in port of the DE2-115 board and connect a speaker to the line-out port.

Page 81: Usb Paintbrush

• Page 82 Nios II Workspace: DE2_115_NIOS_HOST_MOUSE_VGA\Software  Connect a USB Mouse to the USB Host Connector (type A) of the DE2-115 board  Connect the VGA output of the DE2-115 board to a VGA monitor (both LCD and CRT type of monitors should work) ...

Page 83: Usb Device

• Page 84  Bit stream used: DE2_115_NIOS_DEVICE_LED.sof  Nios II Workspace: DE2_115_NIOS_DEVICE_LED\Software  Borland C++ Software Driver: DE2_115_NIOS_DEVICE_LED\SW  Connect the USB Device connector of the DE2-115 board to the host computer using a USB cable (type AB).  Load the bit stream into FPGA(note*) ...

Page 85: A Karaoke Machine

• Page 86  Project directory: DE2_115_i2sound  Bit stream used: DE2_115_i2sound.sof or DE2_115_i2sound.pof  Connect a microphone to the microphone-in port (pink color) on the DE2-115 board  Connect the audio output of a music-player, such as an MP3 player or computer, to the line-in port (blue color) on the DE2-115 board ...

Page 87: Sd Card Demonstration

• Page 88 LED if it fails to parse the FAT file system or if there is no SD Card found in the SD Card socket of the DE2-115 board. If users press KEY3 of the DE2-115 board,...
• Page 89  Make sure Quartus II and Nios II are installed on your PC.  Power on the DE2-115 board.  Connect USB Blaster to the DE2-115 board and install USB Blaster driver if necessary.  Execute the demo batch file “DE2_115_SD_Card.bat” under the batch file folder, DE2_115_SD_CARD\demo_batch.

Page 90: Sd Card Music Player

• Page 91 Figure 6-13 shows the hardware block diagram of this demonstration. The system requires a 50 MHz clock provided from the board. The PLL generates a 100MHz clock for Nios II processor and the other controllers except for the audio controller. The audio chip is controlled by the Audio Controller which is a user-defined SOPC component.
• Page 92 7-segment display, and the LEDs. The top and bottom row of the LCD module will display the file name of the music that is played on the DE2-115 board and the value of music volume, respectively. The 7-segment displays will show the elapsed time of the playing music file. The LED will indicate the audio signal strength.
• Page 93  Connect a headset or speaker to the DE2-115 board and you should be able to hear the music played from the SD Card  Press KEY3 on the DE2-115 board to play the next music file stored in the SD Card.

Page 94: Ps/2 Mouse Demonstration

• Page 95  Data transmit from the device to controller After sending an enabling instruction to the PS/2 mouse at stream mode, the device starts to send displacement data out, which consists of 33 bits. The frame data is cut into three similar slices, each of them containing a start bit (always zero) and eight data bits (with LSB first), one parity check bit (odd check), and one stop bit (always one).
• Page 96 Figure 6-16 Waveforms on two lines while communication taking place  Demonstration Setup, File Locations, and Instructions  Project directory: DE2_115_PS2_DEMO  Bit stream used : DE2_115_PS2_DEMO.sof  Load the bit stream into FPGA by executing DE2_115_PS2_DEMO\demo_batch\DE2_115_PS2_DEMO.bat  Plug in the PS/2 mouse ...

Page 97: Ir Receiver Demonstration

• Page 98 Figure 6-18 Remote controller Table 6-3 Key code information for each Key on remote controller Key Code Key Code Key Code Key Code 0x0F 0x13 0x10 0x12 0x01 0x02 0x03 0x1A 0x04 0x05 0x06 0x1E 0x07 0x08 0x09 0x1B 0x11 0x00 0x17 0x1F...
• Page 99 After the IR receiver on DE2-115 board receives this frame, it will directly transmit that to FPGA. In this demo, the IP of IR receiver controller is implemented in the FPGA. As Figure 6-20 shows, it includes Code Detector, State Machine, and Shift Register. First, the IR receiver demodulates the signal inputs to Code Detector block .The Code Detector block will check the Lead Code and...
• Page 100 We can apply the IR receiver to many applications, such as integrating to the SD Card Demo, and you can also develop other related interesting applications with it.  Demonstration Setup, File Locations, and Instructions  Project directory: DE2_115_IR  Bit stream used: DE2_115_IR.sof ...

Page 101: Music Synthesizer Demonstration

• Page 102  Bit stream used: DE2_115_Synthesizer.sof or DE2-115_Synthesizer.pof  Connect a PS/2 Keyboard to the DE2-115 board.  Connect the VGA output of the DE2-115 board to a VGA monitor (both LCD and CRT type of monitors should work)  Connect the lineout of the DE2-115 board to a speaker.
• Page 103 Table 6-5 Table 6-6 illustrate the usage of the slide switches, push-button switches (KEYs), PS/2 Keyboard.  Slide Switches and Push-buttons switches Table 6-5 Usage of the slide switches and push-buttons switches (KEYs) Signal Name Description KEY[0] Reset Circuit KEY[1] Repeat the Demo Music SW[0] OFF: BRASS, ON: STRING...

Page 104: Audio Recording And Playing

• Page 105 Figure 6-25 Man-Machine Interface of Audio Recorder and Player Figure 6-26 shows the block diagram of the Audio Recorder and Player design. There are hardware and software parts in the block diagram. The software part stores the Nios II program in SRAM. The software part is built by Nios II IDE in C programming language.
• Page 106  Bit stream used: DE2_115_AUDIO.sof  Software Project directory: DE2_115_AUDIO\software\  Connect an Audio Source to the LINE-IN port of the DE2-115 board.  Connect a Microphone to MIC-IN port on the DE2-115 board.  Connect a speaker or headset to LINE-OUT port on the DE2-115 board.

Page 107: Web Server Demonstration

• Page 108 Figure 6-27 MII interface MAC Configuration...
• Page 109 Figure 6-28 RGMII interface MAC Configuration In the MAC Options tab (See Figure 6-29), users should set up proper values for the PHY chip 88E1111. The MDIO Module should be included, as it is used to generate a 2.5MHz MDC clock for the PHY chip from the controller's source clock(here a 100MHz clock source is expected) to divide the MAC control register interface clock to produce the MDC clock output on the MDIO interface.
• Page 110 Figure 6-29 MAC Options Configuration Once the Triple-Speed Ethernet IP configuration has been set and necessary hardware connections have been made as shown in Figure 6-30, click on generate.
• Page 111 Figure 6-30 SOPC Builder Figure 6-31 shows the connections for programmable 10/100Mbps Ethernet operation via MII. Figure 6-31 PHY connected to the MAC via MII Figure 6-32 shows the connections for programmable 10/100/1000Mbps Ethernet operation via RGMII.
• Page 112 Figure 6-33. The top block contains the Nios II processor and the necessary hardware to be implemented into the DE2-115 host board. The software device drivers contain the necessary device drivers needed for the Ethernet and other hardware components to work.
• Page 113 NicheStack™ TCP/IP Stack will start to run for Web Server application. Figure 6-34 describes this demo setup and connections on DE2-115. The Nios II processor is running NicheStack™ on the MicroC/OS-II RTOS. Note: your gateway should support DHCP because it uses DHCP protocol to request a valid IP from the Gateway, or else you would need to reconfigure the system library to use static IP assignment.
• Page 114  You will see the brand new DE2-115 webpage on your computer  On the web page, you could access the DE2-115 board‟s peripherals from the left sidebar or link to external pages from the right sidebar. Try check some LEDs on the left sidebar and then press send will light up the specified LEDs on board.
• Page 115 Note: Or execute DE2_115_Web_Server\<Web Server Mode-Port Specific>\demo_batch\web_server.bat for downloading .sof and .elf files. Figure 6-34 System Principle Diagram Figure 6-35 Served web page for DE2-115...

Page 116: Chapter 7 Appendix

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How to assign different pins in Pin Planner in Quartus?

I am trying to make the 7 segment display of my FPGA work. I found some working code, but I got issues with the pin planner. The FPGA is this , a knockoff Altera Cyclone IV E EP4CE6E22C8. The code :

The code compiles and I can upload it, I just can't change the pins so that they can match the ones of my FPGA. I was thinking to use the dip switches as inputs. Some screenshots below.

To whoever takes sometime to help, thank you!

• 7segmentdisplay

• \$\begingroup\$ As a start, look in the project's .qsf (Quartus Settings File). That will list the pin physical constraints including pin locations. You can edit and save that directly, following the format of the existing pin location constraints, which should be there from what you show. Then try synthesizing that and let us know. \$\endgroup\$ –  TonyM Commented Aug 19, 2019 at 8:35
• \$\begingroup\$ I am sorry, but i am kind of new to this, where can i locate the .qsf file? Also i think that i when started the project i chose the .osf file format, would that be a problem? \$\endgroup\$ –  Rozakos Commented Aug 19, 2019 at 9:06
• \$\begingroup\$ Enter your pins in the Pin Planner Location column. They will be assigned when you rebuild the project. \$\endgroup\$ –  Leon Heller Commented Aug 19, 2019 at 9:34
• \$\begingroup\$ That seems to have done the trick! Thank you very much! Ok one more question, is it possible to set the CLK on HIGH all the time? I guess i could assign it to the dip switch? \$\endgroup\$ –  Rozakos Commented Aug 19, 2019 at 10:09
• \$\begingroup\$ There are several ways of assigning pins - best is to insert them in the code but I've forgotten how to do that. Can't help with your CLK problem. \$\endgroup\$ –  Leon Heller Commented Aug 19, 2019 at 10:20

Enter your pins in the Pin Planner Location column. They will be assigned when you rebuild the project.

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DE1 I/O Pins

Clocks, buttons, switches, and seven segment displays.

The Cyclone II EP2C20F484C7 FPGA on the DE1 logic kit is connected to four seven segment displays, (Hex_0, Hex_1, Hex_2, and Hex_3), ten slide switches (Switch_0 through Switch_9), four push buttons (Key_0 through Key_3), ten red LEDs (Red_LED_0 through Red_LED_9), and eight green LEDs (Green_LED_0 through Green_LED_7).

The slide switches produce logic “1” when pushed away from the edge of the board, and the push buttons produce logic “0” when pressed. The segments of the seven segment displays light up when connected to logic “0,” and the LEDs light up when connected to logic “1”. The following table shows which FPGA pin numbers are connected to these devices.

The segments of a seven-segment display are normally named A–G, starting at the top, going clockwise, and ending with the center segment. The array names in the table refer to the segments using subscript values 0–6 in the same order.

To make the process of pin assignment easier, the following table is in alphabetical order, which should match the order of the pins listed by the Quartus Pin Assignment Editor, provided you name your pins and pin groups alphabetically: Clock… , Green… , Hex_0… , Hex_1… , Hex_2… , Hex_3… , Key… , Red… , and Switch… in that order.

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Altera pin assignment

• Thread starter shaiko
• Start date Jun 17, 2015
• Jun 17, 2015

Advanced Member level 5

Hello, Altera's Quartus has 3 ways to assign pins to the FPGA device: 1. Assignment Editor. 2. Pin Planner. 3. Direct text input into *.QSF. My question: Are these tools synchronized with each other? For example: if I do initial assignments using the Pin Planner and then make changes in the *.QSF file - will the changes in the QSF propagate back to the Pin Planner settings?  

Super Moderator

As long as you save the changes to the QSF, I 'm pretty sure they get loaded for each tool (you may have to close and reopen the tool to get the latest changes), but I might be mis-remembering as it's been 5-6 years since I've used Quartus.  

TrickyDicky

Advanced member level 7.

Any changes you make via assignment editor and pin planner are written to the QSF file (stands for quartus settings file I think). Quartus uses the QSF file to set up the assignment editor and pin planner (and all the other stuff in its gui). Ensure you havent got the project open when you hand edit the .qsf though You can also assign pins via attributes in the HDL.  

TrickyDicky said: Ensure you havent got the project open when you hand edit the .qsf though Click to expand...

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